This invention relates to a direct memory access (DMA) controller not only having a data assembly (or funneling) function but also capable of carrying out transition between channels according to priority levels.
The DMA transfer systems include a dual address mode system which outputs first the address of a source device to transfer data from the source device to the DMA transfer data holding register (temporary register) of a DMA controller and then the address of a destination device to transfer the data from the temporary register to the destination device. Some of the dual address mode DMA controllers have a data assembly function. For example, where a 32-bit DMA controller transfers data from an input/output (I/O) unit with a 8-bit port to a memory with a 32-bit data bus width, four bytes data are transferred to a temporary register in response to DMA requests and, then, all the 32-bit data are transferred at once to predetermined areas of the memory. Where data is transferred from the 32-bit memory to the 8-bit port I/O unit, 3 bytes of data in excess of the necessary 1 byte data are also transferred from the memory to the temporary register in response to the first DMA request, and transfers are carried out from the temporary register to the I/O unit in the subsequent three DMA requests.
The DMA controller having such a data assembly function is provided with temporary registers dedicated for each channel so that channel transition during data assembly is carried out instantly. This is made possible by the fact that the remaining data in channel transition during data assembly is held in the temporary register.
A conventional 2-channel DMA controller will be described with reference to FIGS. 8-13.
FIG. 8 shows a system with a conventional DMA controller. This system includes a 32-bit DMA controller 1, a 32-bit central processing unit (CPU) 2, the first 8-bit input/output unit (I/O) 3, the second 8-bit input/output unit (I/O) 4, a memory 5 with a 32-bit data bus width, a 32-bit data bus for connecting the DMA controller 1, the CPU 2, and the memory 5, the first 8-bit data bus 7 for connecting the first 8-bit I/O unit 3 and the 32-bit data bus 6, the second 8-bit data bus 8 for connecting the second 8-bit I/O unit 4 and the 32-bit data bus, the first and second 32-bit (four byte) long temporary registers 11 and 12 provided within the DMA controller 1, and the first and second memory areas 51 and 52 within the memory 5.
The DMA controller 1 is programmed to perform DMA transfers between the I/O unit 3 and the memory area 51 (the leading address 1a) and between the I/O unit 4 and the memory area 52 with the aid of each of the temporary registers 11 and 12 and to assign a higher priority to the DMA transfers on the side of the I/O unit 4 than on the side of the I/O unit 3. For the purpose of simplification, the path from the I/O unit 3 to the temporary register 11 to the memory area 51 is hereinafter called "channel 1" and the path from the I/O unit 4 to the temporary register 12 to the memory area 52 is hereinafter called "channel 2."
FIG. 9 shows in a block form the essential part of the conventional DMA controller 1, which includes a transfer request control 13 to control DMA transfer requests output by each I/O unit 3, 4 or software (memory-to-memory DMA transfer) according to predetermined priority levels for carrying out DMA request or channel designation; registers 14 and 15 in which DMA control information, such as a source address, a target address, and an I/O-to-memory, memory-to-I/O, or memory-to-memory transfer mode, is set by the CPU 2 for each channel before DMA transfer, and a selector 16 responsive to a channel designation signal from the transfer request control 13 to select the desired control information.
It further includes a DMA transfer control logic 17 which receives a DMA request signal from the transfer request control 13 and controls DMA transfers, such as outputs of source and destination addresses and temporary registers, in response to DMA control information from the register 14 or 15 through the selector 16; and a selector 18 responsive to a channel designation signal from the transfer request control 13 to switch the output of the DMA transfer control logic 17 to either the temporary register 11 or 12.
FIGS. 10-13 illustrate timing of various DMA transfers in the above conventional system, wherein RQ1-1, RQ1-2, . . . represent DMA requests in the channel 1, RQ2-1, RQ2-2, . . . DMA requests in the channel 2, 1-R, 2-R, . . . transfer cycles from the I/O unit 3 or the memory area 51 to the temporary register 11, 1-W, 2-W, . . . transfer cycles from the temporary register 11 to the memory area 51 or the I/O unit 3.
In operation, first of all, explanation is made with reference to FIGS. 10-11, wherein there are no channel transition requests; i.e., no DMA requests in the channel 2 occur during DMA transfer in the channel 1.
FIG. 10 illustrate the case where DMA transfers are made from the I/O unit 3 to the memory area 51. The transfer request control 13 first responds to the DMA request RQ1-1 to set each channel selector 16, 18 to the channel 1, and the DMA transfer control logic 17 transfers 8-bit data to the 8-bit register 1A of the temporary register 11 via the data buses 7, 6. Then, it sequentially responds to the DMA requests RQ1-2, RQ1-3, and RQ1-4 to sequentially transfer the data to respective 8-bit registers 1B, 1C, and 1D (2-R, 3-R, and 4-R). When the data is transferred to the 8-bit register 1D, the 32 bits of data, with which the temporary register 11 is now filled, are transferred all at once to the memory area 51 at the addresses 1a, 1b, 1c, and 1d (1-W). Subsequently, this cycle is repeated. The channel transition due to a channel transition request made during a period between the transfer cycles 1-R and 3-R is called "channel transition during data assembly."
FIG. 11 illustrates the case where DMA transfers are made from the memory area 51 to the I/O unit 3. In response to the first DMA request RQ1-1, 32 bits of data are transferred all at once from the memory area 51 at the addresses 1a, 1b, 1c, and 1d to the temporary register 11 (1-R). Only 8 bits of the data which have been transferred to the 8-bit register 1A of the temporary register 11 are transferred to the I/O unit 3 (1-W). Then, 8-bit data is sequentially transferred to the I/O unit 3 from the respective 8-bit registers 1B, 1C, and 1D of the temporary register 11 according to the DMA requests RQ1-2, RQ1-3, and RQ1-4 (2-W, 3-W, and 4-W). The channel transition due to a channel transition request made during a period between the transfer cycles 1-W and 3-W is called "channel transition during data assembly."
FIGS. 12-13 illustrate the cases where a channel transition request occurs during data assembly for channel transition; i.e., a DMA request in the channel 2 takes place during data assembly in the DMA transfer in the channel 1 for transition to the channel 2.
FIG. 12 illustrates the case where a channel transition request RQ2-1 occurs during the second data transfer (2-R) from the I/O unit 3 to the temporary register 11 in DMA transfer from the I/O unit 3 to the memory area 51. As soon as the 2-R cycle is completed, the transfer request control 13 switches the respective selectors 16 and 18 to the channel 2 for carrying out DMA transfer 10. At this point, the channel 2 uses the dedicated temporary register 12. If there is still the channel-1 DMA request RQ1-3 when all channel-2 DMA requests RQ2 end, transition is made to the channel 1 to continue carrying out DMA transfers (3-R and subsequent transfers).
FIG. 13 illustrates the case where a channel transition request RQ2-1 takes place during the second data transfer (2-W) from the temporary register 11 to the I/O unit 3 in DMA transfer from the memory area 51 to the I/O unit 3. The channel transition is made in the same manner as that of FIG. 12.
As has been described above, the number of temporary registers in the conventional DMA controller must be equal to that of channels, resulting in the increased chip size.